The present invention relates to integrated-circuits and, in particular, to a circuit and method for a power-on reset sequence in integrated circuits.
One problem in the design of integrated circuits is related the power supply Vcc having a voltage below the minimum level required for proper circuit operation. The power supply Vcc has momentary low voltages during start-up, during shut-down and during system transients. The supply voltage may also have a low voltage if a battery is faulty or is aging. A very low value of power-supply voltage can cause spurious operation of the integrated circuit and, consequently, of any device controlled by that integrated circuit. For example, in a nonvolatile memory, a very low value of power-supply voltage during power-up can cause undesired programming or erasure of the device. In turn, undesired programming or erasure causes loss of integrity of data, adversely affecting the operation of any devices dependent on that data.
There is a need for an improved detection circuit to furnish a signal indicating that the power-supply voltage is below the minimum level for the proper operation of the integrated-circuit system. That signal could then be used to inhibit spurious operation of particular electronic systems within the integrated circuit. Ideally, such detection circuitry should function in a "static" manner, detecting both rising and falling transitions of a power supply through the minimum level for operation.
Prior-art circuitry includes use of bipolar devices to implement a voltage reference function for detection. Other prior-an circuitry includes use of a dynamic detection design that requires a latching circuit or a very large capacitor. The prior art circuitry fails to detect transient loss of the power-supply voltage after an initial power-up condition has occurred. In addition, many of the prior-art power-up circuits require the power-supply voltage to drop substantially lower than the initial detection level for a long period of time before being sensed. Also, some prior-art circuits detect only the rising-edge state of the switched power-supply voltage.
Prior-art circuits and methods include those described in the following articles: (1) "Power Supply Voltage Monitors Maintain Microprocessor Data Integrity "; Larry Shorthill; PCIM; June 1990; (2) "Circuit resets CMOS uPs"; Hans Eichel; EDN; Mar. 22, 1984; and (3) "Reset circuit solves brownout problems"; Damian Bonicatto; EDN; Oct. 16 1986. Other prior-art circuits are described in the following patents: (1) U.S. Pat. No. 4,558,233 issued Dec. 10, 1985, entitled "CMOS Power-On Reset Pulse Generating Circuit with Extended Reset Pulse Duration"; (2) U.S. Pat. No. 4,633,107 issued Dec. 30, 1986, entitled "CMOS Power-UP Reset Circuit for Gate Arrays and Standard Cells"; (3) U.S. Pat. No. 5,111,067 issued May 5, 1992, entitled "Power UP Reset Circuit"; (4) U.S. Pat. No. 4,698,531 issued Oct. 6, 1987, entitled "Power-On Reset Circuit"; (5) U.S. Pat. No. 4,746,822 issued May 24, 1988, entitled "CMOS Power-On Reset Circuit"; (6) U.S. Pat. No. 4,812,679 issued Mar. 14, 1989, entitled "Power-On Reset Circuit"; (7) U.S. Pat. No. 4,885,476 issued Dec. 5, 1989, entitled "Power-On Reset Circuit"; (8) U.S. Pat. No. 4,888,497 issued Dec. 19, 1989 entitled "Generator of Reset Pulses Upon the Rise of the Power Supply for CMOS-Type Integrated Circuits"; and (9) U.S. Pat. No. 4,888,498 issued Dec. 19, 1989, entitled "Integrated-Circuit Power-Up Pulse Generator Circuit".